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Date: 05 December 2008
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Georgia Tech’s Researchers have developed a novel fabrication method of copper connections for high-speed computing  

Topic Name: Georgia Tech’s Researchers have developed a novel fabrication method of copper connections for high-speed computing

Category: Bioelectronics

Research persons: Paul Kohl, Thomas L. Gossage chair

Location: Georgia Institute of Technology, United States

Details

Georgia Tech’s Researchers have developed a novel fabrication method of copper connections for high-speed computing

As computers become more complex, the demand increases for more connections between computer chips and external circuitry such as a motherboard or wireless card. And as the integrated circuits become more advanced, maximizing their performance requires better connections that operate at higher frequencies with less loss.

Improving these two types of connections will increase the amount and speed of information that can be sent throughout a computer, according to Paul Kohl, Thomas L. Gossage chair and Regents’ professor in Georgia Tech’s School of Chemical and Biomolecular Engineering. Kohl presented his work in these areas at the Materials Research Society fall meeting.

The vertical connections between chips and boards are currently formed by melting tin solder between the two pieces and adding glue to hold everything together. Kohl’s research shows that replacing the solder ball connections with copper pillars creates stronger connections and the ability to create more connections.

“Circuitry and computer chips are made with copper lines on them, so we thought we should make the connection between the two with copper also,” said Kohl.

Solder and copper can both tolerate misalignment between two pieces being connected, according to Kohl, but copper is more conductive and creates a stronger bond.

With funding from the Semiconductor Research Corporation (SRC), Kohl and graduate student Tyler Osborn have developed a novel fabrication method to create all-copper connections between computer chips and external circuitry.

The researchers first electroplate a bump of copper onto the surface of both pieces, a process that uses electrical current to coat an electrically conductive object with metal. Then, a solid copper connection between the two bumps is formed by electroless plating, which involves several simultaneous reactions that occur in an aqueous solution without the use of external electrical current.

Since the pillar, which is the same thickness as a dollar bill, is fragile at room temperature, the researchers anneal it, or heat it in an oven for an hour to remove defects and generate a strong solid copper piece. Osborn found that strong bonds were formed at an annealing temperature of 180 degrees Celsius. He has also been investigating how misalignments between the two copper bumps affect pillar strength.

“I’ve also studied the optimal shape for the connections so that they’re flexible and mechanically reliable, yet still have good electrical properties so that we can transmit these high frequency signals without noise,” said Osborn.

The researchers have been working with Texas Instruments, Intel Corporation and Applied Materials to perfect and test their technology. Jim Meindl, director of Georgia Tech’s Microelectronics Research Center and professor in the School of Electrical and Computer Engineering, and Sue Ann Allen, professor in the School of Chemical and Biomolecular Engineering, have also collaborated on the work.

In addition to this new method for making vertical connections between chips and external circuitry, Kohl is also developing an improved signal transmission line with the help of graduate student Todd Spencer.

“Several very long communication pathways exist inside a computer that require a very high performance electrical line that can transmit at higher frequencies over long distances,” explained Spencer.

This is especially important in high-performance servers and routers where inter-chip distances can be large and signal strength may be significantly degraded. Kohl and Spencer have developed a new way to link high-speed signals between chips using an organic substrate, with funding from the Interconnect Focus Center, one of the Semiconductor Research Corporation/Defense Advanced Research Projects Agency (DARPA) Focus Center Research Programs.

Fabrication begins with an epoxy fiberglass substrate with copper lines on one side. The substrate is coated with a polymer and the areas without copper lines are exposed to ultraviolet (UV) light, which disintegrates the polymer where it’s not wanted. Then, the researchers coat the substrate with another polymer that hardens when exposed to UV light. Layers of titanium and copper are added on top of each copper line. When the layered substrate is heated at 180 degrees Celsius, the first polymer layer decomposes into carbon dioxide and acetone, which diffuse out leaving an air pocket.

“The amount of electrical loss relates to the connection’s sensitivity at higher frequencies,” explained Spencer. “Just having this air pocket there reduces our signal loss greatly.”

The researchers are currently designing a coaxial cable for this chip-to-chip signal link, which should greatly increase the maximum signal frequency the connection can carry.

Companies that make computer chips and package them into a device are very interested in these technologies, said Kohl.

“If these connections can be produced at a reasonable cost, they could be very important in the future because you’re giving the customer a better product for the same cost,” said Kohl.

Note for Semiconductor Device Fabrication
Semiconductor device fabrication is the process used to create chips, the integrated circuits that are present in everyday electrical and electronic devices. It is a multiple-step sequence of photographic and chemical processing steps during which electronic circuits are gradually created on a wafer made of pure semiconducting material. Silicon is the most commonly used semiconductor material today, along with various compound semiconductors.
The entire manufacturing process from start to packaged chips ready for shipment takes six to eight weeks and is performed in highly specialized facilities referred to as fabs.
In semiconductor device fabrication, the various processing steps fall into four general categories: deposition, removal, patterning, and modification of electrical properties.
Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies consist of physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others. 
Removal processes are any that remove material from the wafer either in bulk or selective form and consist primarily of etch processes, both wet etching and dry etching such as reactive ion etch (RIE). Chemical-mechanical planarization (CMP) is also a removal process used between levels. 
Patterning covers the series of processes that shape or alter the existing shape of the deposited materials and is generally referred to as lithography. For example, in conventional lithography, the wafer is coated with a chemical called a “photoresist”. The photoresist is exposed by a “stepper”, a machine that focuses, aligns, and moves the mask, exposing select portions of the wafer to short wavelength light. The unexposed regions are washed away by a developer solution. After etching or other processing, the remaining photoresist is removed by plasma ashing. 
Modification of electrical properties has historically consisted of doping transistor sources and drains originally by diffusion furnaces and later by ion implantation. These doping processes are followed by furnace anneal or in advanced devices, by rapid thermal anneal (RTA) which serve to activate the implanted dopants. Modification of electrical properties now also extends to reduction of dielectric constant in low-k insulating materials via exposure to ultraviolet light in UV processing (UVP).

Note for Coaxial Cable
Coaxial cable is an electrical cable consisting of an inner conductor or several uninsulated conductors tightly twisted together, often surrounded by an insulating spacer, surrounded by an outer cylindrical conducting shield (sheath), and usually surrounded by a final insulating layer (jacket). The term coaxial comes from the inner conductor and the outer shield sharing ("co-") the same axis. It is often used as a high-frequency transmission line to carry a high-frequency or broadband signal but may also be used for frequencies as low as audio frequency. The electromagnetic field carrying the signal exists (ideally) only in the space between the inner and outer conductors. The shielding reduces interference from external electromagnetic fields, although coax cable does radiate energy, shielding does somewhat reduce the possibility of a transmitting device causing undesired interference through transmission line leakage.
The construction of coaxial cables varies substantially. Design choices affect the size, flexibility, and loss characteristics of the cable. The inner conductor might be a solid wire or stranded. To get better high-frequency performance, the inner conductor may be silver plated. Sometimes copper-plated iron wire is used as an inner conductor.
The insulator surrounding the inner conductor also has variations. The insulator is a dielectric, and the properties of dielectric control some electrical properties of the cable. A common choice is a solid polyethylene insulator. Lower-loss cables will use a foam polyethylene insulator. Solid Teflon is also used as an insulator. Some coaxial lines use air (or some other gas) and have spacers to keep the inner conductor from touching the shield.
There is also a lot of variety in the shield. Convention coaxial cable had braided copper wire forming the shield. That allowed the cable to be flexible, but it also means there are gaps in the shield layer. It also means the inner dimension of the shield varies slightly because the braid cannot be flat. Sometimes the braid is silver plated. For better shield performance, some cables have a double-layer shield. The shield might be just two braids, but it is more common now to have a thin foil shield covered by a wire braid. Some cables may invest in more than two shield layers. Other shield designs sacrifice flexibility for better performance; some shields are a solid metal tube. Those cables cannot take sharp bends: the shield kinks. Many CATV distribution systems used such cables.

About Semiconductor Research Corporation
Semiconductor Research Corporation was the chip industry's first research consortium. A non-profit founded in 1982 and based in North Carolina, USA, SRC networks with more than 100 universities globally. The consortium manages a broad program of basic and applied university research on semiconductors on behalf of its members.
SRC has three subsidiaries -- Global Research Corporation (GRC) that drives near-term materials, metrology and patterning progress, Focus Center Research Programs (FCRP) that support future generations of IC requirements, and Nanoelectronics Research Initiative (NRI) that is responsible for determining the post-CMOS information element by 2020.
Leveraging their participation, the member companies direct and receive early access to the research results. Members also cultivate early interaction with the thousands of students who collaborate in the work. These companies are currently members of the SRC:
Advanced Micro Devices 
Applied Materials 
Axcelis Technologies 
Cadence Design Systems 
Freescale Semiconductor 
Hewlett-Packard 
IBM 
Intel 
LSI Logic 
Mentor Graphics 
Novellus Systems 
Rohm and Haas Electronic Materials 
Texas Instruments 
Tokyo Electron Limited

In figure 1, Graduate student Todd Spencer and Regents' professor Paul Kohl have developed an improved signal transmission line, made of an organic substrate, to link high-speed signals between computer chips.

In figure 2, Scanning electron microscope image of two copper pillars bonded together using a novel fabrication technique. Placing these all-copper connections between computer chips and external circuitry will lead to increased computing speeds.

In figure 3, Graduate student Tyler Osborn and Regents' professor Paul Kohl have developed a novel fabrication method to create all-copper connections between computer chips and external circuitry. Improving these connections will increase the amount and speed of information that can be sent throughout a computer.


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