Trade.Information

Position Description:

Perform custom layout and verification of high performance RF IC products designed in BiCMOS/CMOS technologies. Responsibilities include transistor level RF and analog cell layout and verification, floor planning, top level routing and tapeout activities. The layout engineer will work closely with design engineers to produce layouts optimized for performance, power and size; will take ownership of all aspects of the layout process including final layout data verification to insure successful implementation of RF IC products.



Qualifications:

It is expected the candidate has 2 ? 5 years working experience in RF/analog/mixed-signal IC layout. The candidate is familiar with advanced RF BiCMOS/CMOS processes, proficient with the Cadence tools and physical design/verification flow; has hands-on layout skills in RF/analog IC environments with the ability to recognize in schematics the need for circuit matching, gradient concerns, data timing and to be able to layout to these issues accordingly. The candidate has the ability to work independently, pays attention to detail, and is well organized. The education requirement for the candidate is BS or an associate degree in Science/Engineering.