Trade.Information

Job Requirements :
BSEE (MSEE Preferred), 8+ years experience

Job purpose: To perform various SoC design and DFT tasks. Responsibilities includes IP core ownership, synthesis, static timing analysis, dynamic timing verification, Scan & ATPG, Logic BIST, formal verification at block, core, and chip levels.

Key responsibilities and accountabilities:
1. Verilog RTL design, development, and debug.
2. RTL synthesis (using Synopsys), and netlist ECO modifications.
3. Knowledge of digital video concepts and interfaces.
4. Knowledge of communication systems.
5. Understanding of analog/digital interfaces and techniques.
6. Specific knowledge of DVI/HDMI/UDI/Display Port a plus.
7. Specific knowledge of high speed digital interfaces a plus.
8. Project leadership and accountability a must.
9. Static Timing Analysis (PrimeTime) at core and chip-level, including generation of all constraints and analysis of timing reports.
10. Verification and Simulation (RTL, Gate, IKOS) at core and chip levels.
11. Formal Verification (Formality, Verplex).
12. Generation of ATE (automatic test equipment, manufacturing test) vectors for cores, including interface to the manufacturing test group.
13. Familiarity with test benches and ASIC simulation environment needed.
14. Interface to the layout engineers to perform all timing closure activities.
15. Minimal travel required to interface with core-IP development experts, verification experts, and occasionally ATE and layout personnel.
16. Strong communication skills and willingness to work in a team environment.
 

     Bachelors Degree; EE